In a semiconductor memory device, a cell field consisting of a plurality of memory cells and a matrix of column and row supply lines or word and bit lines, respectively, is usually built up. These supply lines consist of electrically conducting material, with the actual memory cell being positioned at the crosspoints of the supply lines. To perform a change of the information content in a particular memory cell at the addressed crosspoint or to recall the content of the memory cell, the corresponding word and bit lines are selected and impacted either with a write current or with a read current. To this end, the word and bit lines are controlled by appropriate control means and controllers.
A plurality of kinds of semiconductor memories are known, e.g. a RAM (Random Access Memory) comprising a plurality of memory cells that are each equipped with a capacitor which is connected with a so-called selection transistor. By selectively applying a voltage at the corresponding selection transistor, it is possible to store electric charge as an information unit (bit) in the capacitor during a write process. This information content can be recalled again during a read process via the selection transistor.
A RAM memory device is a memory with optional access, i.e. data can be stored under a particular address and can be read out again under this address later. Since it is intended to accommodate as many memory cells as possible in a RAM memory device, one has been trying to realize or scale same as simple as possible and on the smallest possible space.
Another kind of semiconductor memories are SRAMs (Static Random Access Memory), the memory cells of which each comprise a number of, for instance, 6 transistors. Contrary to this, the memory cells of so-called DRAM (Dynamic Random Access Memory) semiconductor memories comprise in general only one single, correspondingly controlled capacitive element, e.g. a trench capacitor, with the capacitance of which one bit each can be stored as charge. This charge, however, remains for a relatively short time only in a DRAM memory cell, so that a so-called “refresh” must be performed regularly, e.g. approximately every 64 ms, wherein the information content is written in the memory cell again. In contrast to that, no “refresh” has to be performed in the case of SRAMs since the data stored in the memory cell remain stored as long as an appropriate supply voltage is fed to the SRAM. In the case of non-volatile memory devices (NVMs), e.g. EPROMs, EEPROMs, and flash memories, the stored data remain, however, stored even when the supply voltage is switched off.
In real systems of non-volatile memory devices, the stored charge, however, will not remain in the capacitor for any long time, which may result in a loss of information. Due to the scaling of modern semiconductor memory devices, the reasons for the loss of information are, on the one hand, based on basic physical effects such as the scattering of charge carriers, the recombination at defective places, and interaction effects. On the other hand, the loss of information is also caused by so-called leaking paths that are generated during the manufacturing or processing of the memory devices, e.g. unsaturated bonds at interfaces between different materials as well as differing structure dimensions due to process fluctuations.
In both cases, these leaking paths result in that the information stored in the capacitor has to be renewed in time before it is lost. The time span, during which sufficiently many charge carriers remain in the capacitor so that they can be read out as the same information as they were written in, is referred to as “retention time”.
The presently established semiconductor memory technologies are consequently based primarily on the principle of charge storage in materials produced by standard CMOS (complement metal oxide semiconductor) processes. The problem of the leaking currents in the memory capacitor existing with the DRAM memory concept, which results in a loss of charge, has so far been solved insufficiently only by the permanent refreshing of the stored charge. The flash memory concept underlies the problem of limited write and read cycles with barrier layers, wherein no optimum solution has been found yet for the high voltages and the slow read and write cycles. Furthermore, the above-mentioned memory concepts (charge trapping, flash and DRAM memories) will, due to their functioning that is based on the storing of charges, presumably meet with physical scaling limits within foreseeable time. Furthermore, in the case of the flash memory concept, the high switching voltages and the limited number of read and write cycles, and in the case of the DRAM memory concept the limited duration of the storage of the charge state constitute additional problems that have not been solved optimally so far.